On Tue, Sep 3, 2024 at 3:53 PM <devel-request@lists.crash-utility.osci.io> wrote:
Date: Tue,  3 Sep 2024 15:51:25 +0800
From: Kuan-Ying Lee <kuan-ying.lee@canonical.com>
Subject: [Crash-utility] [PATCH v2 0/4] arm64: Introduction of support
        16K page with 4-level table
To: kuan-ying.lee@canonical.com,
        devel@lists.crash-utility.osci.io
Message-ID: <20240903075140.37728-1-kuan-ying.lee@canonical.com>

1. Add support to 16K page size and 4-level page table with 48 VA bits.

2. Fix 64K page size with 52 VA bits issue.
   Becuase we cannot use idmap_ptrs_per_pgd to know the size of
   ptrs_per_pgd.

3. Refactor the translation of PTE to physical address and fix
   indent issue.


Thank you for the update, Kuan-Ying.

For the v2: Ack

Lianbo
 
V1->V2:
 - Simplify the PTE_TO_PHYS macro. Thanks Lianbo.

Kuan-Ying Lee (4):
  arm64: fix indent issue and refactor PTE_TO_PHYS
  arm64: use the same expression to indicate ptrs_per_pgd
  arm64: fix 64K page and 52-bits VA support
  arm64: Support 16K page, 48 VA bits and 4 level page table

 arm64.c | 274 +++++++++++++++++++++++++++++++++++++++++---------------
 defs.h  |  33 ++++++-
 2 files changed, 231 insertions(+), 76 deletions(-)

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2.43.0