4:22 p.m.
With the introduction of radix MMU in Power ISA 3.0, there are changes
in kernel page table management accommodating it. This patch series
makes appropriate changes here to work for such kernels. Also, this
series fixes a few bugs along the way. Patches successfully tested on
BOOK3S. It would be great if someone can test these patches on BOOK3E.
The changes effecting BOOK3E are minimal though.
---
Hari Bathini (6):
ppc64: fix vtop page translation for 4K pages
ppc64: Use kernel terminology for each level in 4-level page table
ppc64/book3s: address changes in kernel v4.5
ppc64/book3s: address change in page flags for PowerISA v3.0
ppc64: use physical addresses and unfold pud for 64K page size
ppc64/book3s: support big endian Linux page tables
defs.h | 74 +++++++++-----
ppc64.c | 340 +++++++++++++++++++++++++++++++++++++++++++++++++--------------
tools.c | 16 +++
3 files changed, 332 insertions(+), 98 deletions(-)
--
- Hari
4:23 p.m.
New subject: [PATCH 1/6] ppc64: fix vtop page translation for 4K pages
PUD index size was changed to 9 from 7 since kernel v3.7, but it was
not updated here. Also, currently L4_MASK is set to 0xfff for kernel
v3.10 and above irrespective of page size but it should be 0x1ff for
4K page size and 0xfff for 64K page size. This patch fixes them.
Signed-off-by: Hari Bathini <hbathini(a)linux.vnet.ibm.com>
---
defs.h | 7 ++++++-
ppc64.c | 10 +++++++---
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/defs.h b/defs.h
index adf6156..ea77823 100644
--- a/defs.h
+++ b/defs.h
@@ -3809,6 +3809,7 @@ struct efi_memory_desc_t {
#define PMD_INDEX_SIZE_L4_4K 7
#define PUD_INDEX_SIZE_L4_4K 7
#define PGD_INDEX_SIZE_L4_4K 9
+#define PUD_INDEX_SIZE_L4_4K_3_7 9
#define PTE_SHIFT_L4_4K 17
#define PMD_MASKED_BITS_4K 0
@@ -3829,7 +3830,10 @@ struct efi_memory_desc_t {
#define PD_HUGE 0x8000000000000000
#define HUGE_PTE_MASK 0x03
#define HUGEPD_SHIFT_MASK 0x3f
-#define L4_MASK (THIS_KERNEL_VERSION >= LINUX(3,10,0) ? 0xfff : 0x1ff)
+
+#define L4_MASK \
+ (THIS_KERNEL_VERSION >= LINUX(3,10,0) ? (machdep->ptrs_per_pgd - 1) : 0x1ff)
+
#define L4_OFFSET(vaddr) ((vaddr >> (machdep->machspec->l4_shift)) &
L4_MASK)
#define PGD_OFFSET_L4(vaddr) \
@@ -5674,6 +5678,7 @@ struct machine_specific {
uint l2_index_size;
uint l1_index_size;
+ uint ptrs_per_l4;
uint ptrs_per_l3;
uint ptrs_per_l2;
uint ptrs_per_l1;
diff --git a/ppc64.c b/ppc64.c
index 07508f7..bf0cd82 100644
--- a/ppc64.c
+++ b/ppc64.c
@@ -299,7 +299,10 @@ ppc64_init(int when)
/* 4K pagesize */
m->l1_index_size = PTE_INDEX_SIZE_L4_4K;
m->l2_index_size = PMD_INDEX_SIZE_L4_4K;
- m->l3_index_size = PUD_INDEX_SIZE_L4_4K;
+ if (THIS_KERNEL_VERSION >= LINUX(3,7,0))
+ m->l3_index_size = PUD_INDEX_SIZE_L4_4K_3_7;
+ else
+ m->l3_index_size = PUD_INDEX_SIZE_L4_4K;
m->l4_index_size = PGD_INDEX_SIZE_L4_4K;
m->pte_shift = (machdep->flags & BOOK3E) ?
PTE_SHIFT_L4_BOOK3E_4K : PTE_SHIFT_L4_4K;
@@ -311,8 +314,8 @@ ppc64_init(int when)
m->ptrs_per_l1 = (1 << m->l1_index_size);
m->ptrs_per_l2 = (1 << m->l2_index_size);
m->ptrs_per_l3 = (1 << m->l3_index_size);
-
- machdep->ptrs_per_pgd = m->ptrs_per_l3;
+ m->ptrs_per_l4 = (1 << m->l4_index_size);
+ machdep->ptrs_per_pgd = m->ptrs_per_l4;
/* Compute shifts */
m->l2_shift = m->l1_shift + m->l1_index_size;
@@ -564,6 +567,7 @@ ppc64_dump_machdep_table(ulong arg)
fprintf(fp, " l3_index_size: %d\n",
machdep->machspec->l3_index_size);
fprintf(fp, " l2_index_size: %d\n",
machdep->machspec->l2_index_size);
fprintf(fp, " l1_index_size: %d\n",
machdep->machspec->l1_index_size);
+ fprintf(fp, " ptrs_per_l4: %d\n",
machdep->machspec->ptrs_per_l4);
fprintf(fp, " ptrs_per_l3: %d\n",
machdep->machspec->ptrs_per_l3);
fprintf(fp, " ptrs_per_l2: %d\n",
machdep->machspec->ptrs_per_l2);
fprintf(fp, " ptrs_per_l1: %d\n",
machdep->machspec->ptrs_per_l1);
4:23 p.m.
New subject: [PATCH 2/6] ppc64: Use kernel terminology for each level in 4-level page table
For 4-level page table, we are referring to level3 as PGD instead of
PUD, which is not inline with how kernel refers to it. This patch
corrects it by referring to level4 as PGD and level3 as PUD.
Signed-off-by: Hari Bathini <hbathini(a)linux.vnet.ibm.com>
---
defs.h | 18 ++++--------------
ppc64.c | 62 +++++++++++++++++++++++++++++++-------------------------------
2 files changed, 35 insertions(+), 45 deletions(-)
diff --git a/defs.h b/defs.h
index ea77823..6e537b9 100644
--- a/defs.h
+++ b/defs.h
@@ -3831,12 +3831,13 @@ struct efi_memory_desc_t {
#define HUGE_PTE_MASK 0x03
#define HUGEPD_SHIFT_MASK 0x3f
-#define L4_MASK \
+#define PGD_MASK_L4 \
(THIS_KERNEL_VERSION >= LINUX(3,10,0) ? (machdep->ptrs_per_pgd - 1) : 0x1ff)
-#define L4_OFFSET(vaddr) ((vaddr >> (machdep->machspec->l4_shift)) &
L4_MASK)
-
#define PGD_OFFSET_L4(vaddr) \
+ ((vaddr >> (machdep->machspec->l4_shift)) & PGD_MASK_L4)
+
+#define PUD_OFFSET_L4(vaddr) \
((vaddr >> (machdep->machspec->l3_shift)) &
(machdep->machspec->ptrs_per_l3 - 1))
#define PMD_OFFSET_L4(vaddr) \
@@ -5670,8 +5671,6 @@ struct machine_specific {
ulong hwintrstack[NR_CPUS];
char *hwstackbuf;
uint hwstacksize;
- char *level4;
- ulong last_level4_read;
uint l4_index_size;
uint l3_index_size;
@@ -5708,15 +5707,6 @@ struct machine_specific {
int (*is_vmaddr)(ulong);
};
-#define IS_LAST_L4_READ(l4) ((ulong)(l4) == machdep->machspec->last_level4_read)
-
-#define FILL_L4(L4, TYPE, SIZE) \
- if (!IS_LAST_L4_READ(L4)) { \
- readmem((ulonglong)((ulong)(L4)), TYPE, machdep->machspec->level4, \
- SIZE, "level4 page", FAULT_ON_ERROR); \
- machdep->machspec->last_level4_read = (ulong)(L4); \
- }
-
void ppc64_init(int);
void ppc64_dump_machdep_table(ulong);
#define display_idt_table() \
diff --git a/ppc64.c b/ppc64.c
index bf0cd82..511c189 100644
--- a/ppc64.c
+++ b/ppc64.c
@@ -179,9 +179,9 @@ ppc64_init(int when)
return;
machdep->stacksize = PPC64_STACK_SIZE;
machdep->last_pgd_read = 0;
- machdep->last_pmd_read = 0;
- machdep->last_ptbl_read = 0;
- machdep->machspec->last_level4_read = 0;
+ machdep->last_pud_read = 0;
+ machdep->last_pmd_read = 0;
+ machdep->last_ptbl_read = 0;
machdep->verify_paddr = generic_verify_paddr;
machdep->ptrs_per_pgd = PTRS_PER_PGD;
machdep->flags |= MACHDEP_BT_TEXT;
@@ -223,12 +223,12 @@ ppc64_init(int when)
machdep->pagemask = ~((ulonglong)machdep->pageoffset);
if ((machdep->pgd = (char *)malloc(PAGESIZE())) == NULL)
error(FATAL, "cannot malloc pgd space.");
+ if ((machdep->pud = (char *)malloc(PAGESIZE())) == NULL)
+ error(FATAL, "cannot malloc pud space.");
if ((machdep->pmd = (char *)malloc(PAGESIZE())) == NULL)
error(FATAL, "cannot malloc pmd space.");
if ((machdep->ptbl = (char *)malloc(PAGESIZE())) == NULL)
error(FATAL, "cannot malloc ptbl space.");
- if ((machdep->machspec->level4 = (char *)malloc(PAGESIZE())) == NULL)
- error(FATAL, "cannot malloc level4 space.");
machdep->identity_map_base = symbol_value("_stext");
machdep->is_kvaddr = machdep->machspec->is_kvaddr;
@@ -271,8 +271,8 @@ ppc64_init(int when)
}
if (machdep->flags & VM_ORIG) {
/* pre-2.6.14 layout */
- free(machdep->machspec->level4);
- machdep->machspec->level4 = NULL;
+ free(machdep->pud);
+ machdep->pud = NULL;
machdep->ptrs_per_pgd = PTRS_PER_PGD;
} else {
/* 2.6.14 layout */
@@ -519,10 +519,12 @@ ppc64_dump_machdep_table(ulong arg)
fprintf(fp, "xen_kdump_p2m_create: NULL\n");
fprintf(fp, " line_number_hooks: ppc64_line_number_hooks\n");
fprintf(fp, " last_pgd_read: %lx\n", machdep->last_pgd_read);
+ fprintf(fp, " last_pud_read: %lx\n", machdep->last_pud_read);
fprintf(fp, " last_pmd_read: %lx\n", machdep->last_pmd_read);
fprintf(fp, " last_ptbl_read: %lx\n", machdep->last_ptbl_read);
fprintf(fp, "clear_machdep_cache: ppc64_clear_machdep_cache()\n");
fprintf(fp, " pgd: %lx\n", (ulong)machdep->pgd);
+ fprintf(fp, " pud: %lx\n", (ulong)machdep->pud);
fprintf(fp, " pmd: %lx\n", (ulong)machdep->pmd);
fprintf(fp, " ptbl: %lx\n", (ulong)machdep->ptbl);
fprintf(fp, " ptrs_per_pgd: %d\n", machdep->ptrs_per_pgd);
@@ -561,8 +563,6 @@ ppc64_dump_machdep_table(ulong arg)
fprintf(fp, "\n");
fprintf(fp, " hwstackbuf: %lx\n",
(ulong)machdep->machspec->hwstackbuf);
fprintf(fp, " hwstacksize: %d\n",
machdep->machspec->hwstacksize);
- fprintf(fp, " level4: %lx\n",
(ulong)machdep->machspec->level4);
- fprintf(fp, " last_level4_read: %lx\n",
(ulong)machdep->machspec->last_level4_read);
fprintf(fp, " l4_index_size: %d\n",
machdep->machspec->l4_index_size);
fprintf(fp, " l3_index_size: %d\n",
machdep->machspec->l3_index_size);
fprintf(fp, " l2_index_size: %d\n",
machdep->machspec->l2_index_size);
@@ -687,53 +687,53 @@ ppc64_vtop(ulong vaddr, ulong *pgd, physaddr_t *paddr, int verbose)
static int
ppc64_vtop_level4(ulong vaddr, ulong *level4, physaddr_t *paddr, int verbose)
{
- ulong *level4_dir;
- ulong *page_dir;
+ ulong *pgdir;
+ ulong *page_upper;
ulong *page_middle;
ulong *page_table;
- ulong level4_pte, pgd_pte, pmd_pte;
+ ulong pgd_pte, pud_pte, pmd_pte;
ulong pte;
uint hugepage_type = 0; /* 0: regular entry; 1: huge pte; 2: huge pd */
if (verbose)
fprintf(fp, "PAGE DIRECTORY: %lx\n", (ulong)level4);
- level4_dir = (ulong *)((ulong *)level4 + L4_OFFSET(vaddr));
- FILL_L4(PAGEBASE(level4), KVADDR, PAGESIZE());
- level4_pte = ULONG(machdep->machspec->level4 + PAGEOFFSET(level4_dir));
+ pgdir = (ulong *)((ulong *)level4 + PGD_OFFSET_L4(vaddr));
+ FILL_PGD(PAGEBASE(level4), KVADDR, PAGESIZE());
+ pgd_pte = ULONG(machdep->pgd + PAGEOFFSET(pgdir));
if (verbose)
- fprintf(fp, " L4: %lx => %lx\n", (ulong)level4_dir, level4_pte);
- if (!level4_pte)
+ fprintf(fp, " PGD: %lx => %lx\n", (ulong)pgdir, pgd_pte);
+ if (!pgd_pte)
return FALSE;
- hugepage_type = get_ptetype(level4_pte);
+ hugepage_type = get_ptetype(pgd_pte);
if (hugepage_type) {
- pte = level4_pte;
+ pte = pgd_pte;
goto out;
}
/* Sometimes we don't have level3 pagetable entries */
if (machdep->machspec->l3_index_size != 0) {
- page_dir = (ulong *)((ulong *)level4_pte + PGD_OFFSET_L4(vaddr));
- FILL_PGD(PAGEBASE(level4_pte), KVADDR, PAGESIZE());
- pgd_pte = ULONG(machdep->pgd + PAGEOFFSET(page_dir));
+ page_upper = (ulong *)((ulong *)pgd_pte + PUD_OFFSET_L4(vaddr));
+ FILL_PUD(PAGEBASE(pgd_pte), KVADDR, PAGESIZE());
+ pud_pte = ULONG(machdep->pud + PAGEOFFSET(page_upper));
if (verbose)
- fprintf(fp, " PGD: %lx => %lx\n", (ulong)page_dir, pgd_pte);
- if (!pgd_pte)
+ fprintf(fp, " PUD: %lx => %lx\n", (ulong)page_upper, pud_pte);
+ if (!pud_pte)
return FALSE;
- hugepage_type = get_ptetype(pgd_pte);
+ hugepage_type = get_ptetype(pud_pte);
if (hugepage_type) {
- pte = pgd_pte;
+ pte = pud_pte;
goto out;
}
} else {
- pgd_pte = level4_pte;
+ pud_pte = pgd_pte;
}
- page_middle = (ulong *)((ulong *)pgd_pte + PMD_OFFSET_L4(vaddr));
- FILL_PMD(PAGEBASE(pgd_pte), KVADDR, PAGESIZE());
+ page_middle = (ulong *)((ulong *)pud_pte + PMD_OFFSET_L4(vaddr));
+ FILL_PMD(PAGEBASE(pud_pte), KVADDR, PAGESIZE());
pmd_pte = ULONG(machdep->pmd + PAGEOFFSET(page_middle));
if (verbose)
@@ -2967,8 +2967,8 @@ ppc64_init_cpu_info(void)
void
ppc64_clear_machdep_cache(void)
{
- if (machdep->machspec->last_level4_read != vt->kernel_pgd[0])
- machdep->machspec->last_level4_read = 0;
+ if (machdep->last_pgd_read != vt->kernel_pgd[0])
+ machdep->last_pgd_read = 0;
}
static int
4:23 p.m.
New subject: [PATCH 3/6] ppc64/book3s: address changes in kernel v4.5
Starting with kernel v4.5, _PAGE_COHERENT page flag is no longer used.
In kernel v4.5, a new page flag _PAGE_PTE is introduced to distinguish
between PTEs and pointers. Also, pte RPN shift value for 4K page size
is increased by one to accommodate page soft dirty tracking. This patch
addresses these changes here. While we are here, address a TODO for huge
pages and also, replace all instances of pte_shift with pte_rpn_shift to
be in sync with how it is referred to in the kernel.
Signed-off-by: Hari Bathini <hbathini(a)linux.vnet.ibm.com>
---
defs.h | 17 +++++---
ppc64.c | 137 +++++++++++++++++++++++++++++++++++++++++++++++++--------------
2 files changed, 116 insertions(+), 38 deletions(-)
diff --git a/defs.h b/defs.h
index 6e537b9..ce49f18 100644
--- a/defs.h
+++ b/defs.h
@@ -3787,7 +3787,7 @@ struct efi_memory_desc_t {
#define PMD_MASK (~((1UL << PMD_SHIFT) - 1))
/* shift to put page number into pte */
-#define PTE_SHIFT 16
+#define PTE_RPN_SHIFT_DEFAULT 16
#define PMD_TO_PTEPAGE_SHIFT 2 /* Used for 2.6 or later */
#define PTE_INDEX_SIZE 9
@@ -3810,7 +3810,8 @@ struct efi_memory_desc_t {
#define PUD_INDEX_SIZE_L4_4K 7
#define PGD_INDEX_SIZE_L4_4K 9
#define PUD_INDEX_SIZE_L4_4K_3_7 9
-#define PTE_SHIFT_L4_4K 17
+#define PTE_RPN_SHIFT_L4_4K 17
+#define PTE_RPN_SHIFT_L4_4K_4_5 18
#define PMD_MASKED_BITS_4K 0
/* 64K pagesize */
@@ -3821,10 +3822,10 @@ struct efi_memory_desc_t {
#define PTE_INDEX_SIZE_L4_64K_3_10 8
#define PMD_INDEX_SIZE_L4_64K_3_10 10
#define PGD_INDEX_SIZE_L4_64K_3_10 12
-#define PTE_SHIFT_L4_64K_V1 32
-#define PTE_SHIFT_L4_64K_V2 30
-#define PTE_SHIFT_L4_BOOK3E_64K 28
-#define PTE_SHIFT_L4_BOOK3E_4K 24
+#define PTE_RPN_SHIFT_L4_64K_V1 32
+#define PTE_RPN_SHIFT_L4_64K_V2 30
+#define PTE_RPN_SHIFT_L4_BOOK3E_64K 28
+#define PTE_RPN_SHIFT_L4_BOOK3E_4K 24
#define PMD_MASKED_BITS_64K 0x1ff
#define PD_HUGE 0x8000000000000000
@@ -3843,6 +3844,7 @@ struct efi_memory_desc_t {
#define PMD_OFFSET_L4(vaddr) \
((vaddr >> (machdep->machspec->l2_shift)) &
(machdep->machspec->ptrs_per_l2 - 1))
+#define _PAGE_PTE (machdep->machspec->_page_pte) /* distinguishes
PTEs from pointers */
#define _PAGE_PRESENT (machdep->machspec->_page_present) /* software: pte
contains a translation */
#define _PAGE_USER (machdep->machspec->_page_user) /* matches one of
the PP bits */
#define _PAGE_RW (machdep->machspec->_page_rw) /* software: user
write access allowed */
@@ -5687,13 +5689,14 @@ struct machine_specific {
uint l2_shift;
uint l1_shift;
- uint pte_shift;
+ uint pte_rpn_shift;
uint l2_masked_bits;
int vmemmap_cnt;
int vmemmap_psize;
ulong vmemmap_base;
struct ppc64_vmemmap *vmemmap_list;
+ ulong _page_pte;
ulong _page_present;
ulong _page_user;
ulong _page_rw;
diff --git a/ppc64.c b/ppc64.c
index 511c189..6b89eaa 100644
--- a/ppc64.c
+++ b/ppc64.c
@@ -72,33 +72,63 @@ static inline uint get_ptetype(ulong pte)
return pte_type;
}
-static int is_hugepage(ulong pte)
+static inline int is_hugepage(ulong pte)
{
- /*
- * leaf pte for huge page, bottom two bits != 00
- */
- return ((pte & HUGE_PTE_MASK) != 0x0);
+ if ((machdep->flags & BOOK3E) ||
+ (THIS_KERNEL_VERSION < LINUX(3,10,0))) {
+ /*
+ * hugepage support via hugepd for book3e and
+ * also kernel v3.9 & below.
+ */
+ return 0;
+
+ } else if (THIS_KERNEL_VERSION >= LINUX(4,5,0)) {
+ /*
+ * leaf pte for huge page, if _PAGE_PTE is set.
+ */
+ return !!(pte & _PAGE_PTE);
+
+ } else { /* BOOK3S, kernel v3.10 - v4.4 */
+
+ /*
+ * leaf pte for huge page, bottom two bits != 00
+ */
+ return ((pte & HUGE_PTE_MASK) != 0x0);
+ }
}
static inline int is_hugepd(ulong pte)
{
- if (THIS_KERNEL_VERSION >= LINUX(3,10,0)) {
+ if ((machdep->flags & BOOK3E) ||
+ (THIS_KERNEL_VERSION < LINUX(3,10,0)))
+ return ((pte & PD_HUGE) == 0x0);
+
+ else if (THIS_KERNEL_VERSION >= LINUX(4,5,0)) {
+ /*
+ * hugepd pointer, if _PAGE_PTE is not set and
+ * hugepd shift mask is set.
+ */
+ return (!(pte & _PAGE_PTE) &&
+ ((pte & HUGEPD_SHIFT_MASK) != 0));
+
+ } else { /* BOOK3S, kernel v3.10 - v4.4 */
+
/*
* hugepd pointer, bottom two bits == 00 and next 4 bits
* indicate size of table
- */
+ */
return (((pte & HUGE_PTE_MASK) == 0x0) &&
((pte & HUGEPD_SHIFT_MASK) != 0));
- } else
- return ((pte & PD_HUGE) == 0x0);
+ }
}
static inline ulong hugepage_dir(ulong pte)
{
- if (THIS_KERNEL_VERSION >= LINUX(3,10,0))
- return (ulong)(pte & ~HUGEPD_SHIFT_MASK);
- else
+ if ((machdep->flags & BOOK3E) ||
+ (THIS_KERNEL_VERSION < LINUX(3,10,0)))
return (ulong)((pte & ~HUGEPD_SHIFT_MASK) | PD_HUGE);
+ else
+ return (ulong)(pte & ~HUGEPD_SHIFT_MASK);
}
static int book3e_is_kvaddr(ulong addr)
@@ -122,7 +152,8 @@ struct machine_specific ppc64_machine_specific = {
.hwintrstack = { 0 },
.hwstackbuf = 0,
.hwstacksize = 0,
- .pte_shift = PTE_SHIFT,
+ .pte_rpn_shift = PTE_RPN_SHIFT_DEFAULT,
+ ._page_pte = 0x0UL,
._page_present = 0x1UL,
._page_user = 0x2UL,
._page_rw = 0x4UL,
@@ -140,7 +171,8 @@ struct machine_specific book3e_machine_specific = {
.hwintrstack = { 0 },
.hwstackbuf = 0,
.hwstacksize = 0,
- .pte_shift = PTE_SHIFT_L4_BOOK3E_64K,
+ .pte_rpn_shift = PTE_RPN_SHIFT_L4_BOOK3E_64K,
+ ._page_pte = 0x0UL,
._page_present = 0x1UL,
._page_user = 0xCUL,
._page_rw = 0x30UL,
@@ -262,6 +294,31 @@ ppc64_init(int when)
break;
case POST_GDB:
+ if (!(machdep->flags & BOOK3E)) {
+ struct machine_specific *m = machdep->machspec;
+
+ /*
+ * Starting with v3.14 we no longer use _PAGE_COHERENT
+ * bit as it is always set on hash64 and on platforms
+ * that cannot always set it, _PAGE_NO_CACHE and
+ * _PAGE_WRITETHRU can be used to infer it.
+ */
+ if (THIS_KERNEL_VERSION >= LINUX(3,14,0))
+ m->_page_coherent = 0x0UL;
+
+ /*
+ * In kernel v4.5, _PAGE_PTE bit is introduced to
+ * distinguish PTEs from pointers.
+ */
+ if (THIS_KERNEL_VERSION >= LINUX(4,5,0)) {
+ m->_page_pte = 0x1UL;
+ m->_page_present = 0x2UL;
+ m->_page_user = 0x4UL;
+ m->_page_rw = 0x8UL;
+ m->_page_guarded = 0x10UL;
+ }
+ }
+
if (!(machdep->flags & (VM_ORIG|VM_4_LEVEL))) {
if (THIS_KERNEL_VERSION >= LINUX(2,6,14)) {
machdep->flags |= VM_4_LEVEL;
@@ -292,8 +349,8 @@ ppc64_init(int when)
m->l4_index_size = PGD_INDEX_SIZE_L4_64K;
}
if (!(machdep->flags & BOOK3E))
- m->pte_shift = symbol_exists("demote_segment_4k") ?
- PTE_SHIFT_L4_64K_V2 : PTE_SHIFT_L4_64K_V1;
+ m->pte_rpn_shift = symbol_exists("demote_segment_4k") ?
+ PTE_RPN_SHIFT_L4_64K_V2 : PTE_RPN_SHIFT_L4_64K_V1;
m->l2_masked_bits = PMD_MASKED_BITS_64K;
} else {
/* 4K pagesize */
@@ -304,8 +361,11 @@ ppc64_init(int when)
else
m->l3_index_size = PUD_INDEX_SIZE_L4_4K;
m->l4_index_size = PGD_INDEX_SIZE_L4_4K;
- m->pte_shift = (machdep->flags & BOOK3E) ?
- PTE_SHIFT_L4_BOOK3E_4K : PTE_SHIFT_L4_4K;
+ if (machdep->flags & BOOK3E)
+ m->pte_rpn_shift = PTE_RPN_SHIFT_L4_BOOK3E_4K;
+ else
+ m->pte_rpn_shift = THIS_KERNEL_VERSION >= LINUX(4,5,0) ?
+ PTE_RPN_SHIFT_L4_4K_4_5 : PTE_RPN_SHIFT_L4_4K;
m->l2_masked_bits = PMD_MASKED_BITS_4K;
}
@@ -575,7 +635,7 @@ ppc64_dump_machdep_table(ulong arg)
fprintf(fp, " l3_shift: %d\n",
machdep->machspec->l3_shift);
fprintf(fp, " l2_shift: %d\n",
machdep->machspec->l2_shift);
fprintf(fp, " l1_shift: %d\n",
machdep->machspec->l1_shift);
- fprintf(fp, " pte_shift: %d\n",
machdep->machspec->pte_shift);
+ fprintf(fp, " pte_rpn_shift: %d\n",
machdep->machspec->pte_rpn_shift);
fprintf(fp, " l2_masked_bits: %x\n",
machdep->machspec->l2_masked_bits);
fprintf(fp, " vmemmap_base: ");
if (machdep->machspec->vmemmap_base)
@@ -662,7 +722,7 @@ ppc64_vtop(ulong vaddr, ulong *pgd, physaddr_t *paddr, int verbose)
if (!(pte & _PAGE_PRESENT)) {
if (pte && verbose) {
fprintf(fp, "\n");
- ppc64_translate_pte(pte, 0, PTE_SHIFT);
+ ppc64_translate_pte(pte, 0, PTE_RPN_SHIFT_DEFAULT);
}
return FALSE;
}
@@ -670,11 +730,11 @@ ppc64_vtop(ulong vaddr, ulong *pgd, physaddr_t *paddr, int verbose)
if (!pte)
return FALSE;
- *paddr = PAGEBASE(PTOB(pte >> PTE_SHIFT)) + PAGEOFFSET(vaddr);
+ *paddr = PAGEBASE(PTOB(pte >> PTE_RPN_SHIFT_DEFAULT)) + PAGEOFFSET(vaddr);
if (verbose) {
fprintf(fp, " PAGE: %lx\n\n", PAGEBASE(*paddr));
- ppc64_translate_pte(pte, 0, PTE_SHIFT);
+ ppc64_translate_pte(pte, 0, PTE_RPN_SHIFT_DEFAULT);
}
return TRUE;
@@ -693,6 +753,7 @@ ppc64_vtop_level4(ulong vaddr, ulong *level4, physaddr_t *paddr, int
verbose)
ulong *page_table;
ulong pgd_pte, pud_pte, pmd_pte;
ulong pte;
+ uint pdshift;
uint hugepage_type = 0; /* 0: regular entry; 1: huge pte; 2: huge pd */
if (verbose)
@@ -709,6 +770,7 @@ ppc64_vtop_level4(ulong vaddr, ulong *level4, physaddr_t *paddr, int
verbose)
hugepage_type = get_ptetype(pgd_pte);
if (hugepage_type) {
pte = pgd_pte;
+ pdshift = machdep->machspec->l4_shift;
goto out;
}
@@ -726,6 +788,7 @@ ppc64_vtop_level4(ulong vaddr, ulong *level4, physaddr_t *paddr, int
verbose)
hugepage_type = get_ptetype(pud_pte);
if (hugepage_type) {
pte = pud_pte;
+ pdshift = machdep->machspec->l3_shift;
goto out;
}
} else {
@@ -745,6 +808,7 @@ ppc64_vtop_level4(ulong vaddr, ulong *level4, physaddr_t *paddr, int
verbose)
hugepage_type = get_ptetype(pmd_pte);
if (hugepage_type) {
pte = pmd_pte;
+ pdshift = machdep->machspec->l2_shift;
goto out;
}
@@ -763,7 +827,7 @@ ppc64_vtop_level4(ulong vaddr, ulong *level4, physaddr_t *paddr, int
verbose)
if (!(pte & _PAGE_PRESENT)) {
if (pte && verbose) {
fprintf(fp, "\n");
- ppc64_translate_pte(pte, 0, machdep->machspec->pte_shift);
+ ppc64_translate_pte(pte, 0, machdep->machspec->pte_rpn_shift);
}
return FALSE;
}
@@ -781,13 +845,22 @@ out:
* in this directory for all the huge pages
* in this huge page directory.
*/
- readmem(hugepage_dir(pte), KVADDR, &pte, sizeof(pte),
- "hugepd_entry", RETURN_ON_ERROR);
+ ulong hugepd = hugepage_dir(pte);
+
+ readmem(hugepd, KVADDR, &pte, sizeof(pte),
+ "hugepd_entry", RETURN_ON_ERROR);
+
+ if (verbose)
+ fprintf(fp, " HUGE PD: %lx => %lx\n", hugepd, pte);
+
+ if (!pte)
+ return FALSE;
}
- /* TODO: get page offset for huge pages based on page size */
- *paddr = PAGEBASE(PTOB(pte >> machdep->machspec->pte_shift));
+
+ *paddr = PAGEBASE(PTOB(pte >> machdep->machspec->pte_rpn_shift))
+ + (vaddr & ((1UL << pdshift) - 1));
} else {
- *paddr = PAGEBASE(PTOB(pte >> machdep->machspec->pte_shift))
+ *paddr = PAGEBASE(PTOB(pte >> machdep->machspec->pte_rpn_shift))
+ PAGEOFFSET(vaddr);
}
@@ -796,7 +869,7 @@ out:
fprintf(fp, " HUGE PAGE: %lx\n\n", PAGEBASE(*paddr));
else
fprintf(fp, " PAGE: %lx\n\n", PAGEBASE(*paddr));
- ppc64_translate_pte(pte, 0, machdep->machspec->pte_shift);
+ ppc64_translate_pte(pte, 0, machdep->machspec->pte_rpn_shift);
}
return TRUE;
@@ -1251,7 +1324,7 @@ ppc64_get_task_pgd(ulong task)
* If a physaddr pointer is passed in, don't print anything.
*/
static int
-ppc64_translate_pte(ulong pte, void *physaddr, ulonglong pte_shift)
+ppc64_translate_pte(ulong pte, void *physaddr, ulonglong pte_rpn_shift)
{
int c, len1, len2, len3, others, page_present;
char buf[BUFSIZE];
@@ -1262,7 +1335,7 @@ ppc64_translate_pte(ulong pte, void *physaddr, ulonglong pte_shift)
char *arglist[MAXARGS];
ulong paddr;
- paddr = PTOB(pte >> pte_shift);
+ paddr = PTOB(pte >> pte_rpn_shift);
page_present = (pte & _PAGE_PRESENT);
if (physaddr) {
@@ -1309,6 +1382,8 @@ ppc64_translate_pte(ulong pte, void *physaddr, ulonglong pte_shift)
others = 0;
if (pte) {
+ if (pte & _PAGE_PTE)
+ fprintf(fp, "%sPTE", others++ ? "|" :
"");
if (pte & _PAGE_PRESENT)
fprintf(fp, "%sPRESENT", others++ ? "|" :
"");
if (pte & _PAGE_USER)
4:23 p.m.
New subject: [PATCH 4/6] ppc64/book3s: address change in page flags for PowerISA v3.0
PowerISA v3.0 CPUs expect _PAGE_PRESENT to be at 0x8000_0000_0000_0000
instead of 0x2 and _PAGE_PTE to be at 0x4000_0000_0000_0000 instead of
0x1 in radix mode. These requirements are accomodated by changing the
flags _PAGE_PRESENT & _PAGE_PTE for 64-bit POWER server processors with
kernel commits 849f86a6 & 84c95756. This patch makes the corresponding
changes here.
Signed-off-by: Hari Bathini <hbathini(a)linux.vnet.ibm.com>
---
ppc64.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/ppc64.c b/ppc64.c
index 6b89eaa..8733d64 100644
--- a/ppc64.c
+++ b/ppc64.c
@@ -317,6 +317,16 @@ ppc64_init(int when)
m->_page_rw = 0x8UL;
m->_page_guarded = 0x10UL;
}
+
+ /*
+ * Starting with kernel v4.6, to accommodate both
+ * radix and hash MMU modes in a single kernel,
+ * _PAGE_PTE & _PAGE_PRESENT page flags are changed.
+ */
+ if (THIS_KERNEL_VERSION >= LINUX(4,6,0)) {
+ m->_page_pte = 0x1UL << 62;
+ m->_page_present = 0x1UL << 63;
+ }
}
if (!(machdep->flags & (VM_ORIG|VM_4_LEVEL))) {
@@ -1336,7 +1346,7 @@ ppc64_translate_pte(ulong pte, void *physaddr, ulonglong
pte_rpn_shift)
ulong paddr;
paddr = PTOB(pte >> pte_rpn_shift);
- page_present = (pte & _PAGE_PRESENT);
+ page_present = !!(pte & _PAGE_PRESENT);
if (physaddr) {
*((ulong *)physaddr) = paddr;
4:23 p.m.
New subject: [PATCH 5/6] ppc64: use physical addresses and unfold pud for 64K page size
Starting with kernel v4.6, page tables store physical addresses
in upper page table tree levels for book3s. In book3s, Page table
for 64K pagesize is switched to 4-level (pud not folded anymore) to
support both hash and radix page tables in a single kernel. Also,
the pmd masked bits value is changed since kernel v4.5 for book3e.
This patch updates the corresponding changes here.
Signed-off-by: Hari Bathini <hbathini(a)linux.vnet.ibm.com>
---
defs.h | 34 +++++++++++++++++---
ppc64.c | 108 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-----
2 files changed, 129 insertions(+), 13 deletions(-)
diff --git a/defs.h b/defs.h
index ce49f18..a56fa65 100644
--- a/defs.h
+++ b/defs.h
@@ -3812,6 +3812,8 @@ struct efi_memory_desc_t {
#define PUD_INDEX_SIZE_L4_4K_3_7 9
#define PTE_RPN_SHIFT_L4_4K 17
#define PTE_RPN_SHIFT_L4_4K_4_5 18
+#define PGD_MASKED_BITS_4K 0
+#define PUD_MASKED_BITS_4K 0
#define PMD_MASKED_BITS_4K 0
/* 64K pagesize */
@@ -3822,15 +3824,30 @@ struct efi_memory_desc_t {
#define PTE_INDEX_SIZE_L4_64K_3_10 8
#define PMD_INDEX_SIZE_L4_64K_3_10 10
#define PGD_INDEX_SIZE_L4_64K_3_10 12
+#define PMD_INDEX_SIZE_L4_64K_4_6 5
+#define PUD_INDEX_SIZE_L4_64K_4_6 5
#define PTE_RPN_SHIFT_L4_64K_V1 32
#define PTE_RPN_SHIFT_L4_64K_V2 30
#define PTE_RPN_SHIFT_L4_BOOK3E_64K 28
#define PTE_RPN_SHIFT_L4_BOOK3E_4K 24
+#define PGD_MASKED_BITS_64K 0
+#define PUD_MASKED_BITS_64K 0x1ff
#define PMD_MASKED_BITS_64K 0x1ff
+#define PMD_MASKED_BITS_64K_3_11 0xfff
+#define PMD_MASKED_BITS_BOOK3E_64K_4_5 0x7ff
+#define PGD_MASKED_BITS_64K_4_6 0xc0000000000000ffUL
+#define PUD_MASKED_BITS_64K_4_6 0xc0000000000000ffUL
+#define PMD_MASKED_BITS_64K_4_6 0xc0000000000000ffUL
+
+#define PTE_RPN_MASK_DEFAULT 0xffffffffffffffffUL
+#define PTE_RPN_SIZE_L4_4_6 (PAGESIZE() == PPC64_64K_PAGE_SIZE ? 41 : 45)
+#define PTE_RPN_MASK_L4_4_6 (((1UL << PTE_RPN_SIZE_L4_4_6) - 1) <<
PAGESHIFT())
+#define PTE_RPN_SHIFT_L4_4_6 PAGESHIFT()
#define PD_HUGE 0x8000000000000000
#define HUGE_PTE_MASK 0x03
#define HUGEPD_SHIFT_MASK 0x3f
+#define HUGEPD_ADDR_MASK (0x0fffffffffffffffUL & ~HUGEPD_SHIFT_MASK)
#define PGD_MASK_L4 \
(THIS_KERNEL_VERSION >= LINUX(3,10,0) ? (machdep->ptrs_per_pgd - 1) : 0x1ff)
@@ -3855,6 +3872,9 @@ struct efi_memory_desc_t {
#define _PAGE_DIRTY (machdep->machspec->_page_dirty) /* C: page changed
*/
#define _PAGE_ACCESSED (machdep->machspec->_page_accessed) /* R: page
referenced */
+#define PTE_RPN_MASK (machdep->machspec->pte_rpn_mask)
+#define PTE_RPN_SHIFT (machdep->machspec->pte_rpn_shift)
+
#define TIF_SIGPENDING (2)
#define SWP_TYPE(entry) (((entry) >> 1) & 0x7f)
@@ -5690,7 +5710,10 @@ struct machine_specific {
uint l1_shift;
uint pte_rpn_shift;
- uint l2_masked_bits;
+ ulong pte_rpn_mask;
+ ulong pgd_masked_bits;
+ ulong pud_masked_bits;
+ ulong pmd_masked_bits;
int vmemmap_cnt;
int vmemmap_psize;
@@ -5714,10 +5737,11 @@ void ppc64_init(int);
void ppc64_dump_machdep_table(ulong);
#define display_idt_table() \
error(FATAL, "-d option is not applicable to PowerPC architecture\n")
-#define KSYMS_START (0x1)
-#define VM_ORIG (0x2)
-#define VMEMMAP_AWARE (0x4)
-#define BOOK3E (0x8)
+#define KSYMS_START (0x1)
+#define VM_ORIG (0x2)
+#define VMEMMAP_AWARE (0x4)
+#define BOOK3E (0x8)
+#define PHYS_ENTRY_L4 (0x10)
#define REGION_SHIFT (60UL)
#define REGION_ID(addr) (((unsigned long)(addr)) >> REGION_SHIFT)
diff --git a/ppc64.c b/ppc64.c
index 8733d64..4e18513 100644
--- a/ppc64.c
+++ b/ppc64.c
@@ -59,6 +59,9 @@ static uint get_ptetype(ulong pte);
static int is_hugepage(ulong pte);
static int is_hugepd(ulong pte);
static ulong hugepage_dir(ulong pte);
+static ulong pgd_page_vaddr_l4(ulong pgd);
+static ulong pud_page_vaddr_l4(ulong pud);
+static ulong pmd_page_vaddr_l4(ulong pmd);
static inline uint get_ptetype(ulong pte)
{
@@ -127,10 +130,57 @@ static inline ulong hugepage_dir(ulong pte)
if ((machdep->flags & BOOK3E) ||
(THIS_KERNEL_VERSION < LINUX(3,10,0)))
return (ulong)((pte & ~HUGEPD_SHIFT_MASK) | PD_HUGE);
- else
+ else if (machdep->flags & PHYS_ENTRY_L4)
+ return PTOV(pte & ~HUGEPD_ADDR_MASK);
+ else /* BOOK3S, kernel v3.10 - v4.4 */
return (ulong)(pte & ~HUGEPD_SHIFT_MASK);
}
+static inline ulong pgd_page_vaddr_l4(ulong pgd)
+{
+ ulong pgd_val;
+
+ pgd_val = (pgd & ~machdep->machspec->pgd_masked_bits);
+ if (machdep->flags & PHYS_ENTRY_L4) {
+ /*
+ * physical address is stored starting from kernel v4.6
+ */
+ pgd_val = PTOV(pgd_val);
+ }
+
+ return pgd_val;
+}
+
+static inline ulong pud_page_vaddr_l4(ulong pud)
+{
+ ulong pud_val;
+
+ pud_val = (pud & ~machdep->machspec->pud_masked_bits);
+ if (machdep->flags & PHYS_ENTRY_L4) {
+ /*
+ * physical address is stored starting from kernel v4.6
+ */
+ pud_val = PTOV(pud_val);
+ }
+
+ return pud_val;
+}
+
+static inline ulong pmd_page_vaddr_l4(ulong pmd)
+{
+ ulong pmd_val;
+
+ pmd_val = (pmd & ~machdep->machspec->pmd_masked_bits);
+ if (machdep->flags & PHYS_ENTRY_L4) {
+ /*
+ * physical address is stored starting from kernel v4.6
+ */
+ pmd_val = PTOV(pmd_val);
+ }
+
+ return pmd_val;
+}
+
static int book3e_is_kvaddr(ulong addr)
{
return (addr >= BOOK3E_VMBASE);
@@ -322,10 +372,12 @@ ppc64_init(int when)
* Starting with kernel v4.6, to accommodate both
* radix and hash MMU modes in a single kernel,
* _PAGE_PTE & _PAGE_PRESENT page flags are changed.
+ * Also, page table entries store physical addresses.
*/
if (THIS_KERNEL_VERSION >= LINUX(4,6,0)) {
m->_page_pte = 0x1UL << 62;
m->_page_present = 0x1UL << 63;
+ machdep->flags |= PHYS_ENTRY_L4;
}
}
@@ -346,7 +398,14 @@ ppc64_init(int when)
struct machine_specific *m = machdep->machspec;
if (machdep->pagesize == 65536) {
/* 64K pagesize */
- if (THIS_KERNEL_VERSION >= LINUX(3,10,0)) {
+ if (!(machdep->flags & BOOK3E) &&
+ (THIS_KERNEL_VERSION >= LINUX(4,6,0))) {
+ m->l1_index_size = PTE_INDEX_SIZE_L4_64K_3_10;
+ m->l2_index_size = PMD_INDEX_SIZE_L4_64K_4_6;
+ m->l3_index_size = PUD_INDEX_SIZE_L4_64K_4_6;
+ m->l4_index_size = PGD_INDEX_SIZE_L4_64K_3_10;
+
+ } else if (THIS_KERNEL_VERSION >= LINUX(3,10,0)) {
m->l1_index_size = PTE_INDEX_SIZE_L4_64K_3_10;
m->l2_index_size = PMD_INDEX_SIZE_L4_64K_3_10;
m->l3_index_size = PUD_INDEX_SIZE_L4_64K;
@@ -358,10 +417,27 @@ ppc64_init(int when)
m->l3_index_size = PUD_INDEX_SIZE_L4_64K;
m->l4_index_size = PGD_INDEX_SIZE_L4_64K;
}
+
if (!(machdep->flags & BOOK3E))
m->pte_rpn_shift = symbol_exists("demote_segment_4k") ?
PTE_RPN_SHIFT_L4_64K_V2 : PTE_RPN_SHIFT_L4_64K_V1;
- m->l2_masked_bits = PMD_MASKED_BITS_64K;
+
+ if (!(machdep->flags & BOOK3E) &&
+ (THIS_KERNEL_VERSION >= LINUX(4,6,0))) {
+ m->pgd_masked_bits = PGD_MASKED_BITS_64K_4_6;
+ m->pud_masked_bits = PUD_MASKED_BITS_64K_4_6;
+ m->pmd_masked_bits = PMD_MASKED_BITS_64K_4_6;
+ } else {
+ m->pgd_masked_bits = PGD_MASKED_BITS_64K;
+ m->pud_masked_bits = PUD_MASKED_BITS_64K;
+ if ((machdep->flags & BOOK3E) &&
+ (THIS_KERNEL_VERSION >= LINUX(4,5,0)))
+ m->pmd_masked_bits = PMD_MASKED_BITS_BOOK3E_64K_4_5;
+ else if (THIS_KERNEL_VERSION >= LINUX(3,11,0))
+ m->pmd_masked_bits = PMD_MASKED_BITS_64K_3_11;
+ else
+ m->pmd_masked_bits = PMD_MASKED_BITS_64K;
+ }
} else {
/* 4K pagesize */
m->l1_index_size = PTE_INDEX_SIZE_L4_4K;
@@ -371,12 +447,22 @@ ppc64_init(int when)
else
m->l3_index_size = PUD_INDEX_SIZE_L4_4K;
m->l4_index_size = PGD_INDEX_SIZE_L4_4K;
+
if (machdep->flags & BOOK3E)
m->pte_rpn_shift = PTE_RPN_SHIFT_L4_BOOK3E_4K;
else
m->pte_rpn_shift = THIS_KERNEL_VERSION >= LINUX(4,5,0) ?
PTE_RPN_SHIFT_L4_4K_4_5 : PTE_RPN_SHIFT_L4_4K;
- m->l2_masked_bits = PMD_MASKED_BITS_4K;
+ m->pgd_masked_bits = PGD_MASKED_BITS_4K;
+ m->pud_masked_bits = PUD_MASKED_BITS_4K;
+ m->pmd_masked_bits = PMD_MASKED_BITS_4K;
+ }
+
+ m->pte_rpn_mask = PTE_RPN_MASK_DEFAULT;
+ if (!(machdep->flags & BOOK3E) &&
+ (THIS_KERNEL_VERSION >= LINUX(4,6,0))) {
+ m->pte_rpn_mask = PTE_RPN_MASK_L4_4_6;
+ m->pte_rpn_shift = PTE_RPN_SHIFT_L4_4_6;
}
/* Compute ptrs per each level */
@@ -645,8 +731,11 @@ ppc64_dump_machdep_table(ulong arg)
fprintf(fp, " l3_shift: %d\n",
machdep->machspec->l3_shift);
fprintf(fp, " l2_shift: %d\n",
machdep->machspec->l2_shift);
fprintf(fp, " l1_shift: %d\n",
machdep->machspec->l1_shift);
+ fprintf(fp, " pte_rpn_mask: %lx\n",
machdep->machspec->pte_rpn_mask);
fprintf(fp, " pte_rpn_shift: %d\n",
machdep->machspec->pte_rpn_shift);
- fprintf(fp, " l2_masked_bits: %x\n",
machdep->machspec->l2_masked_bits);
+ fprintf(fp, " pgd_masked_bits: %lx\n",
machdep->machspec->pgd_masked_bits);
+ fprintf(fp, " pud_masked_bits: %lx\n",
machdep->machspec->pud_masked_bits);
+ fprintf(fp, " pmd_masked_bits: %lx\n",
machdep->machspec->pmd_masked_bits);
fprintf(fp, " vmemmap_base: ");
if (machdep->machspec->vmemmap_base)
fprintf(fp, "%lx\n", machdep->machspec->vmemmap_base);
@@ -786,6 +875,7 @@ ppc64_vtop_level4(ulong vaddr, ulong *level4, physaddr_t *paddr, int
verbose)
/* Sometimes we don't have level3 pagetable entries */
if (machdep->machspec->l3_index_size != 0) {
+ pgd_pte = pgd_page_vaddr_l4(pgd_pte);
page_upper = (ulong *)((ulong *)pgd_pte + PUD_OFFSET_L4(vaddr));
FILL_PUD(PAGEBASE(pgd_pte), KVADDR, PAGESIZE());
pud_pte = ULONG(machdep->pud + PAGEOFFSET(page_upper));
@@ -805,6 +895,7 @@ ppc64_vtop_level4(ulong vaddr, ulong *level4, physaddr_t *paddr, int
verbose)
pud_pte = pgd_pte;
}
+ pud_pte = pud_page_vaddr_l4(pud_pte);
page_middle = (ulong *)((ulong *)pud_pte + PMD_OFFSET_L4(vaddr));
FILL_PMD(PAGEBASE(pud_pte), KVADDR, PAGESIZE());
pmd_pte = ULONG(machdep->pmd + PAGEOFFSET(page_middle));
@@ -822,7 +913,8 @@ ppc64_vtop_level4(ulong vaddr, ulong *level4, physaddr_t *paddr, int
verbose)
goto out;
}
- page_table = (ulong *)(pmd_pte & ~(machdep->machspec->l2_masked_bits))
+ pmd_pte = pmd_page_vaddr_l4(pmd_pte);
+ page_table = (ulong *)(pmd_pte)
+ (BTOP(vaddr) & (machdep->machspec->ptrs_per_l1 - 1));
if (verbose)
fprintf(fp, " PMD: %lx => %lx\n",(ulong)page_middle,
@@ -867,10 +959,10 @@ out:
return FALSE;
}
- *paddr = PAGEBASE(PTOB(pte >> machdep->machspec->pte_rpn_shift))
+ *paddr = PAGEBASE(PTOB((pte & PTE_RPN_MASK) >> PTE_RPN_SHIFT))
+ (vaddr & ((1UL << pdshift) - 1));
} else {
- *paddr = PAGEBASE(PTOB(pte >> machdep->machspec->pte_rpn_shift))
+ *paddr = PAGEBASE(PTOB((pte & PTE_RPN_MASK) >> PTE_RPN_SHIFT))
+ PAGEOFFSET(vaddr);
}
4:23 p.m.
New subject: [PATCH 6/6] ppc64/book3s: support big endian Linux page tables
Power ISA 3.0 defines a new MMU mode, known as Radix Tree Translation,
where the hardware can directly operate on the Linux page tables.
However the hardware requires that the page tables be in big endian
format. Starting with kernel v4.7, Linux page tables are big endian
for both radix and hash MMU modes in book3s 64. This patch makes the
corresponding changes here.
Signed-off-by: Hari Bathini <hbathini(a)linux.vnet.ibm.com>
---
defs.h | 2 ++
ppc64.c | 21 +++++++++++++++++----
tools.c | 16 ++++++++++++++++
3 files changed, 35 insertions(+), 4 deletions(-)
diff --git a/defs.h b/defs.h
index a56fa65..0a15798 100644
--- a/defs.h
+++ b/defs.h
@@ -4821,6 +4821,7 @@ int calculate(char *, ulong *, ulonglong *, ulong);
int endian_mismatch(char *, char, ulong);
uint16_t swap16(uint16_t, int);
uint32_t swap32(uint32_t, int);
+uint64_t swap64(uint64_t, int);
ulong *get_cpumask_buf(void);
int make_cpumask(char *, ulong *, int, int *);
size_t strlcpy(char *, char *, size_t);
@@ -5742,6 +5743,7 @@ void ppc64_dump_machdep_table(ulong);
#define VMEMMAP_AWARE (0x4)
#define BOOK3E (0x8)
#define PHYS_ENTRY_L4 (0x10)
+#define SWAP_ENTRY_L4 (0x20)
#define REGION_SHIFT (60UL)
#define REGION_ID(addr) (((unsigned long)(addr)) >> REGION_SHIFT)
diff --git a/ppc64.c b/ppc64.c
index 4e18513..83ebd16 100644
--- a/ppc64.c
+++ b/ppc64.c
@@ -15,7 +15,9 @@
* GNU General Public License for more details.
*/
#ifdef PPC64
+
#include "defs.h"
+#include <endian.h>
static int ppc64_kvtop(struct task_context *, ulong, physaddr_t *, int);
static int ppc64_uvtop(struct task_context *, ulong, physaddr_t *, int);
@@ -379,6 +381,16 @@ ppc64_init(int when)
m->_page_present = 0x1UL << 63;
machdep->flags |= PHYS_ENTRY_L4;
}
+
+ if (THIS_KERNEL_VERSION >= LINUX(4,7,0)) {
+ /*
+ * Starting with kernel v4.7 page table entries
+ * are always big endian on BOOK3S. Set this
+ * flag if kernel is not big endian.
+ */
+ if (__BYTE_ORDER == __LITTLE_ENDIAN)
+ machdep->flags |= SWAP_ENTRY_L4;
+ }
}
if (!(machdep->flags & (VM_ORIG|VM_4_LEVEL))) {
@@ -854,13 +866,14 @@ ppc64_vtop_level4(ulong vaddr, ulong *level4, physaddr_t *paddr, int
verbose)
ulong pte;
uint pdshift;
uint hugepage_type = 0; /* 0: regular entry; 1: huge pte; 2: huge pd */
+ uint swap = !!(machdep->flags & SWAP_ENTRY_L4);
if (verbose)
fprintf(fp, "PAGE DIRECTORY: %lx\n", (ulong)level4);
pgdir = (ulong *)((ulong *)level4 + PGD_OFFSET_L4(vaddr));
FILL_PGD(PAGEBASE(level4), KVADDR, PAGESIZE());
- pgd_pte = ULONG(machdep->pgd + PAGEOFFSET(pgdir));
+ pgd_pte = swap64(ULONG(machdep->pgd + PAGEOFFSET(pgdir)), swap);
if (verbose)
fprintf(fp, " PGD: %lx => %lx\n", (ulong)pgdir, pgd_pte);
if (!pgd_pte)
@@ -878,7 +891,7 @@ ppc64_vtop_level4(ulong vaddr, ulong *level4, physaddr_t *paddr, int
verbose)
pgd_pte = pgd_page_vaddr_l4(pgd_pte);
page_upper = (ulong *)((ulong *)pgd_pte + PUD_OFFSET_L4(vaddr));
FILL_PUD(PAGEBASE(pgd_pte), KVADDR, PAGESIZE());
- pud_pte = ULONG(machdep->pud + PAGEOFFSET(page_upper));
+ pud_pte = swap64(ULONG(machdep->pud + PAGEOFFSET(page_upper)), swap);
if (verbose)
fprintf(fp, " PUD: %lx => %lx\n", (ulong)page_upper, pud_pte);
@@ -898,7 +911,7 @@ ppc64_vtop_level4(ulong vaddr, ulong *level4, physaddr_t *paddr, int
verbose)
pud_pte = pud_page_vaddr_l4(pud_pte);
page_middle = (ulong *)((ulong *)pud_pte + PMD_OFFSET_L4(vaddr));
FILL_PMD(PAGEBASE(pud_pte), KVADDR, PAGESIZE());
- pmd_pte = ULONG(machdep->pmd + PAGEOFFSET(page_middle));
+ pmd_pte = swap64(ULONG(machdep->pmd + PAGEOFFSET(page_middle)), swap);
if (verbose)
fprintf(fp, " PMD: %lx => %lx\n", (ulong)page_middle, pmd_pte);
@@ -921,7 +934,7 @@ ppc64_vtop_level4(ulong vaddr, ulong *level4, physaddr_t *paddr, int
verbose)
(ulong)page_table);
FILL_PTBL(PAGEBASE(pmd_pte), KVADDR, PAGESIZE());
- pte = ULONG(machdep->ptbl + PAGEOFFSET(page_table));
+ pte = swap64(ULONG(machdep->ptbl + PAGEOFFSET(page_table)), swap);
if (verbose)
fprintf(fp, " PTE: %lx => %lx\n", (ulong)page_table, pte);
diff --git a/tools.c b/tools.c
index 1321a9b..53c496f 100644
--- a/tools.c
+++ b/tools.c
@@ -5838,6 +5838,22 @@ swap32(uint32_t val, int swap)
return val;
}
+uint64_t
+swap64(uint64_t val, int swap)
+{
+ if (swap)
+ return (((val & 0x00000000000000ffULL) << 56) |
+ ((val & 0x000000000000ff00ULL) << 40) |
+ ((val & 0x0000000000ff0000ULL) << 24) |
+ ((val & 0x00000000ff000000ULL) << 8) |
+ ((val & 0x000000ff00000000ULL) >> 8) |
+ ((val & 0x0000ff0000000000ULL) >> 24) |
+ ((val & 0x00ff000000000000ULL) >> 40) |
+ ((val & 0xff00000000000000ULL) >> 56));
+ else
+ return val;
+}
+
/*
* Get a sufficiently large buffer for cpumask.
* You should call FREEBUF() on the result when you no longer need it.
10:17 a.m.
----- Original Message -----
With the introduction of radix MMU in Power ISA 3.0, there are
changes
in kernel page table management accommodating it. This patch series
makes appropriate changes here to work for such kernels. Also, this
series fixes a few bugs along the way. Patches successfully tested on
BOOK3S. It would be great if someone can test these patches on BOOK3E.
The changes effecting BOOK3E are minimal though.
Hari,
This looks to be a well-done overhaul of the ppc64 memory management.
I've done some cursory tests on live ppc64 and ppc64le systems, and a few
dumpfiles, e.g., running vtop on user-space and kernel module virtual
addresses, running vm on user-space tasks, etc.
But I don't know how to test these patches on BOOK3E because I don't have
any systems or old vmcores which have the "interrupt_base_book3e" symbol
that is used to set BOOK3E flag. Hopefully somebody on this list, or on
your cc: list, can test the patch-set.
Thanks,
Dave
---
Hari Bathini (6):
ppc64: fix vtop page translation for 4K pages
ppc64: Use kernel terminology for each level in 4-level page table
ppc64/book3s: address changes in kernel v4.5
ppc64/book3s: address change in page flags for PowerISA v3.0
ppc64: use physical addresses and unfold pud for 64K page size
ppc64/book3s: support big endian Linux page tables
defs.h | 74 +++++++++-----
ppc64.c | 340
+++++++++++++++++++++++++++++++++++++++++++++++++--------------
tools.c | 16 +++
3 files changed, 332 insertions(+), 98 deletions(-)
--
- Hari
--
Crash-utility mailing list
Crash-utility(a)redhat.com
https://www.redhat.com/mailman/listinfo/crash-utility
8:12 a.m.
Hari,
The patch-set has been queued for crash-7.1.6:
https://github.com/crash-utility/crash/commit/182914debbb9a2671ef644027fe...
Thanks,
Dave
----- Original Message -----
With the introduction of radix MMU in Power ISA 3.0, there are
changes
in kernel page table management accommodating it. This patch series
makes appropriate changes here to work for such kernels. Also, this
series fixes a few bugs along the way. Patches successfully tested on
BOOK3S. It would be great if someone can test these patches on BOOK3E.
The changes effecting BOOK3E are minimal though.
---
Hari Bathini (6):
ppc64: fix vtop page translation for 4K pages
ppc64: Use kernel terminology for each level in 4-level page table
ppc64/book3s: address changes in kernel v4.5
ppc64/book3s: address change in page flags for PowerISA v3.0
ppc64: use physical addresses and unfold pud for 64K page size
ppc64/book3s: support big endian Linux page tables
defs.h | 74 +++++++++-----
ppc64.c | 340
+++++++++++++++++++++++++++++++++++++++++++++++++--------------
tools.c | 16 +++
3 files changed, 332 insertions(+), 98 deletions(-)
--
- Hari
--
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8 comments
2 participants
participants (2)
-
Dave Anderson -
Hari Bathini