[Crash-utility] [PATCH 6/8] RISCV64: Add 'help -r' command support
Add support form printing out the registers from the dump file.
With the patch, we can get the regs,
crash> help -r
CPU 0:
epc : ffffffff800078f8 ra : ffffffff8008862c sp : ff20000010333b90
gp : ffffffff810dde38 tp : ff6000000226c200 t0 : ffffffff8032be68
t1 : 0720072007200720 t2 : 666666666666663c s0 : ff20000010333cf0
s1 : 0000000000000000 a0 : ff20000010333b98 a1 : 0000000000000001
a2 : 0000000000000010 a3 : 0000000000000000 a4 : 0000000000000000
a5 : ff60000001c78000 a6 : 000000000000003c a7 : ffffffff8035c9a4
s2 : ffffffff810df0a8 s3 : ffffffff810df718 s4 : ff20000010333b98
s5 : 0000000000000000 s6 : 0000000000000007 s7 : ffffffff80c4a468
s8 : 00ffffffca281410 s9 : 0000000000000007 s10: 00aaaaaab5bb6700
s11: 0000000000000001 t3 : ff60000001218f00 t4 : ff60000001218f00
t5 : ff60000001218000 t6 : ff20000010333988
Signed-off-by: Xianting Tian <xianting.tian(a)linux.alibaba.com>
---
riscv64.c | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/riscv64.c b/riscv64.c
index c00ce90..475dc98 100644
--- a/riscv64.c
+++ b/riscv64.c
@@ -1309,6 +1309,44 @@ riscv64_init(int when)
void
riscv64_display_regs_from_elf_notes(int cpu, FILE *ofp)
{
+ const struct machine_specific *ms = machdep->machspec;
+ struct riscv64_register *regs;
+
+ if (!ms->crash_task_regs) {
+ error(INFO, "registers not collected for cpu %d\n", cpu);
+ return;
+ }
+
+ regs = &ms->crash_task_regs[cpu];
+ if (!regs->regs[RISCV64_REGS_SP] && !regs->regs[RISCV64_REGS_EPC]) {
+ error(INFO, "registers not collected for cpu %d\n", cpu);
+ return;
+ }
+
+ /* Print riscv64 32 regs */
+ fprintf(ofp,
+ "epc : " REG_FMT " ra : " REG_FMT " sp : " REG_FMT
"\n"
+ " gp : " REG_FMT " tp : " REG_FMT " t0 : " REG_FMT
"\n"
+ " t1 : " REG_FMT " t2 : " REG_FMT " s0 : " REG_FMT
"\n"
+ " s1 : " REG_FMT " a0 : " REG_FMT " a1 : " REG_FMT
"\n"
+ " a2 : " REG_FMT " a3 : " REG_FMT " a4 : " REG_FMT
"\n"
+ " a5 : " REG_FMT " a6 : " REG_FMT " a7 : " REG_FMT
"\n"
+ " s2 : " REG_FMT " s3 : " REG_FMT " s4 : " REG_FMT
"\n"
+ " s5 : " REG_FMT " s6 : " REG_FMT " s7 : " REG_FMT
"\n"
+ " s8 : " REG_FMT " s9 : " REG_FMT " s10: " REG_FMT
"\n"
+ " s11: " REG_FMT " t3 : " REG_FMT " t4 : " REG_FMT
"\n"
+ " t5 : " REG_FMT " t6 : " REG_FMT "\n",
+ regs->regs[0], regs->regs[1], regs->regs[2],
+ regs->regs[3], regs->regs[4], regs->regs[5],
+ regs->regs[6], regs->regs[7], regs->regs[8],
+ regs->regs[9], regs->regs[10], regs->regs[11],
+ regs->regs[12], regs->regs[13], regs->regs[14],
+ regs->regs[15], regs->regs[16], regs->regs[17],
+ regs->regs[18], regs->regs[19], regs->regs[20],
+ regs->regs[21], regs->regs[22], regs->regs[23],
+ regs->regs[24], regs->regs[25], regs->regs[26],
+ regs->regs[27], regs->regs[28], regs->regs[29],
+ regs->regs[30], regs->regs[31]);
}
#else /* !RISCV64 */
--
2.17.1