This patch add support fleescale ppce500mc in E500 processor chipset. And make platform specific code shape-up so that new support can get easy. Todo: vtop for kernel vaddr in ppce500mc can not work out yet. crash> vtop c0000000 VIRTUAL PHYSICAL c0000000 0 PAGE DIRECTORY: c08d1000 PGD: c08d2800 => 0 # Not mapped from PGD. - linux/arch/powerpc/mm/fsl_booke_mmu.c I think if kernel use TLBCAM's fixed map, page table setting are not required? I'll make up fsl-booke specific physaddr search method later. Thanks, Toshi Toshikazu Nakayama (5): ppc32: handle PTE size by using gdb datatype request ppc32: shrink machine_specific ppc32: handle greater PTE_RPN_SHIFT than PAGE_SHIFT ppc32: add E500 processor probe function ppc32: cleanup page table code defs.h | 59 ++++++++++++++++++++++---------- ppc.c | 118 +++++++++++++++++++++++++++++++++++++-------------------------- 2 files changed, 109 insertions(+), 68 deletions(-)

On 03/19/2012 03:17 PM, Toshikazu Nakayama wrote: > This patch add support fleescale ppce500mc in E500 processor chipset. > And make platform specific code shape-up so that new support can get easy. > Toshikazu Nakayama-san, The patches look good to me. > + if (machdep->flags& PAE) > pte = ULONGLONG(machdep->ptbl + PAGEOFFSET((ulong)page_table)); May be we could introduce a macro to replace (machdep->flags& PAE) There are quite a lot of places where we use it now. Something like, #define IS_PAE() (machdep->flags& PAE) What do you think ? Reviewed-by: Suzuki K. Poulose<suzuki(a)in.ibm.com>

Thanks Suzuki