subscription policy changed
by Dave Young
Hi list
We get spam emails every some time, it is very annoying. So I have changed the subscription policy to "Confirm then Moderate", hope it can avoid the spams.
First subscribers have to confirm, then a moderator needs to authorize. If the email address is a suspicious one eg. some weird gmail account I will reply with some simple question about what is crash etc to confirm the purpose of the request. Otherwise normally I will just confirm and approve the subscription.
Thanks
Dave
2 hours, 14 minutes
Madagascar Evisa Fee
by a.lexandra.24510.1＠gmail.com
<a href="https://evisa-madagascar.it.com/madagascar-evisa-fee-and-processing-time/">Madagascar eVisa Fee</a> refers to the cost required to process an electronic visa application for traveling to Madagascar. The fee may vary depending on the type of eVisa, duration of stay, nationality, and processing requirements. Applicants are generally required to pay the applicable fee online during the application process. The payment confirms the submission and allows authorities to review the visa request. Travelers should ensure that all information provided is accurate before making payment, as fees may be non-refundable in some cases. Before applying, applicants should check the latest Madagascar eVisa fee details, accepted payment methods, and updated visa regulations for a smooth experience.
3 hours, 49 minutes
[PATCH 1/2] loongarch64: fix SECTION_SIZE_BITS value
by Dave Young
The loongarch64 SECTION_SIZE_BITS does not match the mainline kernel code.
crash test failed with mem_section init failure due to access non exist
memory address for mem sections caused by wrong NR_SECTION_ROOTS
According to Wang Ming, there was some historic reason, upstream kernel
did not take the SECTION_SIZE_BITS 28, but 28 is still better. Downstream
kernels took the 28 as default.
Thus fix this by setting the related values first according to vmcoreinfo
And falling back to the 29 which aligns to current upstrem kernel.
Signed-off-by: Dave Young <yangrr.2009(a)tsinghua.org.cn>
---
[v1->v2: use vmcoreinfo exported value first]
[future work: share code between arches for converting str to number]
defs.h | 2 +-
loongarch64.c | 18 ++++++++++++++++--
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/defs.h b/defs.h
index 134e7597e966..7c25754afbcd 100644
--- a/defs.h
+++ b/defs.h
@@ -3903,7 +3903,7 @@ typedef signed int s32;
#define TIF_SIGPENDING (1)
-#define _SECTION_SIZE_BITS 28
+#define _SECTION_SIZE_BITS 29
#define _MAX_PHYSMEM_BITS 48
#endif /* LOONGARCH64 */
diff --git a/loongarch64.c b/loongarch64.c
index 39a05b854832..c95910f5ea4a 100644
--- a/loongarch64.c
+++ b/loongarch64.c
@@ -1876,6 +1876,8 @@ pt_level_alloc(char **lvl, char *name)
void
loongarch64_init(int when)
{
+ char *string;
+
switch (when) {
case SETUP_ENV:
machdep->process_elf_notes = process_elf64_notes;
@@ -1933,8 +1935,20 @@ loongarch64_init(int when)
break;
case POST_GDB:
- machdep->section_size_bits = _SECTION_SIZE_BITS;
- machdep->max_physmem_bits = _MAX_PHYSMEM_BITS;
+ string = pc->read_vmcoreinfo("NUMBER(SECTION_SIZE_BITS)");
+ if (string) {
+ machdep->section_size_bits = strtoul(string, NULL, 10);
+ free(string);
+ } else
+ machdep->section_size_bits = _SECTION_SIZE_BITS;
+
+
+ string = pc->read_vmcoreinfo("NUMBER(MAX_PHYSMEM_BITS)");
+ if (string) {
+ machdep->max_physmem_bits = strtoul(string, NULL, 10);
+ free(string);
+ } else
+ machdep->max_physmem_bits = _MAX_PHYSMEM_BITS;
if (symbol_exists("irq_desc"))
ARRAY_LENGTH_INIT(machdep->nr_irqs, irq_desc,
--
2.51.1
7 hours, 6 minutes
[PATCH] loongarch64: fix mem section init failure
by Dave Young
The loongarch64 SECTION_SIZE_BITS does not match the mainline kernel code.
crash test failed with mem_section init failure due to access non exist
memory address for mem sections caused by wrong NR_SECTION_ROOTS
Signed-off-by: Dave Young <yangrr.2009(a)tsinghua.org.cn>
---
defs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Index: crash/defs.h
===================================================================
--- crash.orig/defs.h 2026-08-18 09:40:48.392309457 +0800
+++ crash/defs.h 2026-08-24 14:46:52.133057387 +0800
@@ -3903,7 +3903,7 @@
#define TIF_SIGPENDING (1)
-#define _SECTION_SIZE_BITS 28
+#define _SECTION_SIZE_BITS 29
#define _MAX_PHYSMEM_BITS 48
#endif /* LOONGARCH64 */
7 hours, 26 minutes
[PATCH] riscv64: handle leaf page table entries in vtop
by Rui Qi
RISC-V page table entries at any level may be leaf entries when V is
set and any of R/W/X is set. The riscv64 vtop walkers currently treat
non-zero intermediate entries as pointers to the next page table, so a
PMD leaf can be used as a page table address and make vtop fail with a
physical seek error.
Detect leaf entries at PGD/P4D/PUD/PMD levels and translate them using
the page size implied by that level. Continue walking only for non-leaf
table entries.
Signed-off-by: Rui Qi <qirui.001(a)bytedance.com>
---
riscv64.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/riscv64.c b/riscv64.c
index 4dcecc2f6b2c..ca26965421d7 100644
--- a/riscv64.c
+++ b/riscv64.c
@@ -602,6 +602,33 @@ riscv64_translate_pte(ulong pte, void *physaddr, ulonglong unused)
return page_present;
}
+static int
+riscv64_pte_is_leaf(ulong pte)
+{
+ return ((pte & _PAGE_PRESENT) &&
+ (pte & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)));
+}
+
+static int
+riscv64_handle_leaf_pte(ulong pte, ulong vaddr, int shift,
+ physaddr_t *paddr, int verbose)
+{
+ physaddr_t paddr_base, page_mask;
+
+ pte &= PTE_PFN_PROT_MASK;
+ paddr_base = PTOB(pte >> _PAGE_PFN_SHIFT);
+ page_mask = ~(((physaddr_t)1 << shift) - 1);
+ *paddr = (paddr_base & page_mask) + (vaddr & ~page_mask);
+
+ if (verbose) {
+ fprintf(fp, " PAGE: %016llx\n\n",
+ (ulonglong)(*paddr & page_mask));
+ riscv64_translate_pte(pte, 0, 0);
+ }
+
+ return TRUE;
+}
+
static void
riscv64_page_type_init(void)
{
@@ -655,6 +682,9 @@ riscv64_vtop_3level_4k(ulong *pgd, ulong vaddr, physaddr_t *paddr, int verbose)
fprintf(fp, " PGD: %lx => %lx\n", (ulong)pgd_ptr, pgd_val);
if (!pgd_val)
goto no_page;
+ if (riscv64_pte_is_leaf(pgd_val))
+ return riscv64_handle_leaf_pte(pgd_val, vaddr,
+ PGD_SHIFT_L3, paddr, verbose);
pgd_val &= PTE_PFN_PROT_MASK;
pmd_base = (pgd_val >> _PAGE_PFN_SHIFT) << PAGESHIFT();
@@ -666,6 +696,9 @@ riscv64_vtop_3level_4k(ulong *pgd, ulong vaddr, physaddr_t *paddr, int verbose)
fprintf(fp, " PMD: %016lx => %016lx\n", pmd_addr, pmd_val);
if (!pmd_val)
goto no_page;
+ if (riscv64_pte_is_leaf(pmd_val))
+ return riscv64_handle_leaf_pte(pmd_val, vaddr,
+ PMD_SHIFT, paddr, verbose);
pmd_val &= PTE_PFN_PROT_MASK;
pte_base = (pmd_val >> _PAGE_PFN_SHIFT) << PAGESHIFT();
@@ -1237,6 +1270,9 @@ riscv64_vtop_4level_4k(ulong *pgd, ulong vaddr, physaddr_t *paddr, int verbose)
fprintf(fp, " PGD: %lx => %lx\n", (ulong)pgd_ptr, pgd_val);
if (!pgd_val)
goto no_page;
+ if (riscv64_pte_is_leaf(pgd_val))
+ return riscv64_handle_leaf_pte(pgd_val, vaddr,
+ PGD_SHIFT_L4, paddr, verbose);
pgd_val &= PTE_PFN_PROT_MASK;
pud_base = (pgd_val >> _PAGE_PFN_SHIFT) << PAGESHIFT();
@@ -1248,6 +1284,9 @@ riscv64_vtop_4level_4k(ulong *pgd, ulong vaddr, physaddr_t *paddr, int verbose)
fprintf(fp, " PUD: %016lx => %016lx\n", pud_addr, pud_val);
if (!pud_val)
goto no_page;
+ if (riscv64_pte_is_leaf(pud_val))
+ return riscv64_handle_leaf_pte(pud_val, vaddr,
+ PUD_SHIFT, paddr, verbose);
pud_val &= PTE_PFN_PROT_MASK;
pmd_base = (pud_val >> _PAGE_PFN_SHIFT) << PAGESHIFT();
@@ -1259,6 +1298,9 @@ riscv64_vtop_4level_4k(ulong *pgd, ulong vaddr, physaddr_t *paddr, int verbose)
fprintf(fp, " PMD: %016lx => %016lx\n", pmd_addr, pmd_val);
if (!pmd_val)
goto no_page;
+ if (riscv64_pte_is_leaf(pmd_val))
+ return riscv64_handle_leaf_pte(pmd_val, vaddr,
+ PMD_SHIFT, paddr, verbose);
pmd_val &= PTE_PFN_PROT_MASK;
pte_base = (pmd_val >> _PAGE_PFN_SHIFT) << PAGESHIFT();
@@ -1316,6 +1358,9 @@ riscv64_vtop_5level_4k(ulong *pgd, ulong vaddr, physaddr_t *paddr, int verbose)
fprintf(fp, " PGD: %lx => %lx\n", (ulong)pgd_ptr, pgd_val);
if (!pgd_val)
goto no_page;
+ if (riscv64_pte_is_leaf(pgd_val))
+ return riscv64_handle_leaf_pte(pgd_val, vaddr,
+ PGD_SHIFT_L5, paddr, verbose);
pgd_val &= PTE_PFN_PROT_MASK;
p4d_base = (pgd_val >> _PAGE_PFN_SHIFT) << PAGESHIFT();
@@ -1327,6 +1372,9 @@ riscv64_vtop_5level_4k(ulong *pgd, ulong vaddr, physaddr_t *paddr, int verbose)
fprintf(fp, " P4D: %016lx => %016lx\n", p4d_addr, p4d_val);
if (!p4d_val)
goto no_page;
+ if (riscv64_pte_is_leaf(p4d_val))
+ return riscv64_handle_leaf_pte(p4d_val, vaddr,
+ P4D_SHIFT, paddr, verbose);
p4d_val &= PTE_PFN_PROT_MASK;
pud_base = (p4d_val >> _PAGE_PFN_SHIFT) << PAGESHIFT();
@@ -1338,6 +1386,9 @@ riscv64_vtop_5level_4k(ulong *pgd, ulong vaddr, physaddr_t *paddr, int verbose)
fprintf(fp, " PUD: %016lx => %016lx\n", pud_addr, pud_val);
if (!pud_val)
goto no_page;
+ if (riscv64_pte_is_leaf(pud_val))
+ return riscv64_handle_leaf_pte(pud_val, vaddr,
+ PUD_SHIFT, paddr, verbose);
pud_val &= PTE_PFN_PROT_MASK;
pmd_base = (pud_val >> _PAGE_PFN_SHIFT) << PAGESHIFT();
@@ -1349,6 +1400,9 @@ riscv64_vtop_5level_4k(ulong *pgd, ulong vaddr, physaddr_t *paddr, int verbose)
fprintf(fp, " PMD: %016lx => %016lx\n", pmd_addr, pmd_val);
if (!pmd_val)
goto no_page;
+ if (riscv64_pte_is_leaf(pmd_val))
+ return riscv64_handle_leaf_pte(pmd_val, vaddr,
+ PMD_SHIFT, paddr, verbose);
pmd_val &= PTE_PFN_PROT_MASK;
pte_base = (pmd_val >> _PAGE_PFN_SHIFT) << PAGESHIFT();
--
2.20.1
12 hours, 22 minutes
